//--------------------------------------------------------------------------------------------
//: 
//      Component name  : fpmul_stage3
//      Author          : 
//      Company         : 
//
//      Description     : 
//
//
//--------------------------------------------------------------------------------------------


module FPmul_stage3(EXP_in, EXP_neg_stage2, EXP_pos_stage2, SIGN_out_stage2, SIG_in, clk, isINF_stage2, isNaN_stage2, isZ_tab_stage2, EXP_neg, EXP_out_round, EXP_pos, SIGN_out, SIG_out_round, isINF_tab, isNaN, isZ_tab);
   input [7:0]   EXP_in;
   input         EXP_neg_stage2;
   input         EXP_pos_stage2;
   input         SIGN_out_stage2;
   input [27:0]  SIG_in;
   input         clk;
   input         isINF_stage2;
   input         isNaN_stage2;
   input         isZ_tab_stage2;
   output        EXP_neg;
   reg           EXP_neg;
   output [7:0]  EXP_out_round;
   reg [7:0]     EXP_out_round;
   output        EXP_pos;
   reg           EXP_pos;
   output        SIGN_out;
   reg           SIGN_out;
   output [27:0] SIG_out_round;
   reg [27:0]    SIG_out_round;
   output        isINF_tab;
   reg           isINF_tab;
   output        isNaN;
   reg           isNaN;
   output        isZ_tab;
   reg           isZ_tab;
   
   
   wire [7:0]    EXP_out;
   wire [7:0]    EXP_out_norm;
   wire [27:0]   SIG_out;
   wire [27:0]   SIG_out_norm;
   
   
   always @(posedge clk)
      
      begin
         EXP_out_round <= EXP_out;
         SIG_out_round <= SIG_out;
      end
   
   
   always @(posedge clk)
      
      begin
         isINF_tab <= isINF_stage2;
         isNaN <= isNaN_stage2;
         isZ_tab <= isZ_tab_stage2;
         SIGN_out <= SIGN_out_stage2;
         EXP_pos <= EXP_pos_stage2;
         EXP_neg <= EXP_neg_stage2;
      end
   
   
   FPnormalize #(.SIG_width(28)) I9(.SIG_in(SIG_in), .EXP_in(EXP_in), .SIG_out(SIG_out_norm), .EXP_out(EXP_out_norm));
   
   FPround #(.SIG_width(28)) I11(.SIG_in(SIG_out_norm), .EXP_in(EXP_out_norm), .SIG_out(SIG_out), .EXP_out(EXP_out));
   
endmodule
